1. Field
Various embodiments of the present invention relate to a memory device and an operating method thereof.
2. Description of the Related Art
Memory devices include a plurality of memory cells. A memory cell of a memory device, for example, a DRAM, includes a transistor serving as a switch and a capacitor for storing electrical charges corresponding to data. A logic level of the data, which may be high (logic level 1) or low (logic level 0), may depend on the amount of the charges stored in the capacitor.
While data are stored in the form of charges in a memory cell capacitor, theoretically there is no loss of data or current consumption. However, due to a leakage current the charges and therefore the data may be degraded or lost. In order to prevent data loss, memory cells should be read and recharged periodically before the stored data in the capacitor is lost. The operation of reading and recharging the memory cells is commonly referred to as a refresh operation.
In a typical refresh operation, a memory controller applies a refresh command to the memory device repeatedly at a predetermined period which takes into consideration the data retention time of the memory device. For example, when the data retention time of the memory is 64 ms, the entire memory cells in the memory device may be refreshed according to 8,000 times of applications of the refresh command, that is, the memory controller applies 8,000 refresh commands to the memory device for 64 ms. Furthermore, when the data retention times of some memory cells included in the memory device is determined not to reach the predetermined refresh period in a test process employed during manufacturing, the memory device may be considered as defective and may be discarded. When all memory devices including memory cells having insufficient retention times are discarded, the manufacturing yield inevitably decreases.
Furthermore, data retention times of memory cells may be degraded due to a number of factors even after manufacturing, so that memory cells may cause errors even though the memory device may have passed the manufacturing test process.